Stress-reducing structure for electronic devices

ABSTRACT

Electronic apparatus having a heat transfer/stress-reducing layer combined with a device layer and methods of fabricating such electronic apparatus provide a means for incorporating a heat transfer layer in an integrated circuit. A structure with a diamond layer incorporated beneath a device layer provides a heat transfer layer for the structure. In an embodiment, a compliant layer is formed between a diamond layer and a substrate to provide stress reduction. In another embodiment, a diamond layer is formed as a layer of islands of diamond from nucleation centers to provide stress reduction.

TECHNICAL FIELD

Embodiments of the invention relate generally to semiconductorprocessing.

BACKGROUND

As integrated circuits are scaled down allowing the number of electronicdevices on a die to increase, the amount of heat generated during theoperation of these integrated circuits increases. Additional ways toremove the generated heat become necessary. One approach to remove heatis to incorporate material layers in a die that provide thermalconductivity away from the integrated circuits formed on the die.However, the incorporated material layers used should not createadditional problems in the design, operation, or fabrication of theintegrated circuit or die.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an embodiment of an electronic apparatus having asubstrate, a heat transfer/stress-reducing structure on the substrate,and a device layer on the stress-reducing structure, in accordance withthe present invention.

FIGS. 2A-2D show stages for forming an electronic apparatus having adevice layer and a heat transfer/stress-reducing structure, inaccordance with an embodiment of the present invention.

FIG. 3 depicts a formation of a heat transfer/stress-reducing structureand a device layer including additional layers, in accordance with anembodiment of the present invention.

FIG. 4A depicts an embodiment of the structure of FIG. 3 having acompliant layer less than a specified thickness, where a completed dieis bonded to a heat sink, in accordance with the present invention.

FIG. 4B depicts an embodiment of a structure formed using a compliantlayer greater than a specified thickness, where a completed die isbonded to a heat sink, in accordance with the present invention.

FIGS. 5A-5G show stages associated with another embodiment for formingan electronic apparatus having a device layer and a heattransfer/stress-reducing structure, in accordance with the presentinvention.

FIG. 6A depicts the formation of islands of diamond on a substrate inwhich each island of diamond does not contact any other island ofdiamond, in accordance with an embodiment of the present invention.

FIG. 6B depicts the formation of a device layer above islands of diamondin which each island of diamond does not contact any other island ofdiamond, in accordance with an embodiment of the present invention.

FIG. 7 illustrates a block diagram for a system 700 having devices usingan embodiment for a heat transfer/stress-reducing structure combinedwith a device layer, in accordance with the present invention.

DETAILED DESCRIPTION

The following detailed description refers to the accompanying drawingsthat show, by way of illustration, specific details and embodiments inwhich the invention may be practiced. These embodiments are described insufficient detail to enable those skilled in the art to practice thepresent invention. Other embodiments may be utilized and structural,logical, and electrical changes may be made without departing from thescope of the invention. The various embodiments disclosed herein are notnecessarily mutually exclusive, as some disclosed embodiments can becombined with one or more other disclosed embodiments to form newembodiments.

The terms wafer and substrate used in the following description includeany structure having an exposed surface with which to form an integratedcircuit (IC). The term substrate is understood to include semiconductorwafers. The term substrate may also be used to refer to semiconductorstructures during processing, and may include other layers that havebeen fabricated thereupon. Both wafer and substrate may include dopedand undoped semiconductors, epitaxial semiconductor layers supported bya base semiconductor or insulator, as well as other semiconductorstructures well known to one skilled in the art.

The term “horizontal” as used in this application is defined as a planeparallel to the conventional plane or surface of a wafer or substrate,regardless of the orientation of the wafer or substrate. The term“vertical” refers to a direction perpendicular to the horizontal asdefined above. Prepositions, such as “on”, “side” (as in “sidewall”),“higher”, “lower”, “over” and “under” are defined with respect to theconventional plane or surface being on the top surface of the wafer orsubstrate, regardless of the orientation of the wafer or substrate. Thefigures are not drawn to scale and the relative thickness of variouslayers is also not shown in the drawings. The following detaileddescription is, therefore, not to be taken in a limiting sense, and thescope of the embodiments of the present invention is defined only by theappended claims, along with the full scope of equivalents to which suchclaims are entitled.

A structure for an electronic apparatus that includes a layer thatprovides for enhanced heat transfer from a device layer may improve theperformance, reliability, and lifetime for the electronic apparatus. Forinstance, fabricating diamond layers onto silicon substrates for themanufacture of silicon on diamond (SOD) wafers may enhance device speedperformance for structures with diamond layers. However, fabricating theelectronic apparatus having a heat transfer layer and a device layer canintroduce stress between layers in the electronic apparatus, as a resultof the different materials used for the device layer and the heattransfer layer. An example of such an electronic apparatus is a silicondevice layer with a diamond heat transfer layer. An embodiment of thepresent invention includes a heat transfer/stress-reducing layer abovewhich a device layer is formed, where the heat transfer/stress-reducinglayer may include a layer or layers that provide heat transfer from thedevice layer and reduce stress between the various materials comprisingthe die.

A diamond layer with its high thermal conductivity can spread heat outaway from active devices of an integrated circuit. In an embodiment,diamond layers of thicknesses up to 200 microns are formed beneath anactive silicon layer. The fabrication of such a wafer involves thedeposition of a diamond layer onto a silicon substrate and thesubsequent bonding of a single crystal layer above the diamond layer. Inan embodiment, a SOD wafer is formed using a heattransfer/stress-reducing structure to alleviate stress that can beproduced by differences in the coefficients of thermal expansion (CTE)between diamond and silicon, where the CTE of silicon is 2.4×10⁻⁶ cm/(cmK), and the CTE of diamond is 1.1×10⁻⁶ cm/(cm K). Without providingstress reduction, a wafer can bow and warp when the wafer is cooled fromdiamond deposition temperature, typically at around 800° C., to roomtemperature. Electronic apparatus formed using heattransfer/stress-reducing structures of various embodiments as taughtherein eliminate or substantially reduce bowing and warpage of thewafer.

FIG. 1 illustrates an embodiment of an electronic apparatus 100 having asubstrate 105, a heat transfer/stress-reducing structure 100 onsubstrate 105, and a device layer 115 on heat transfer/stress-reducingstructure 110. In an embodiment, heat transfer/stress-reducing structure110 includes a compliant layer and a diamond layer on the compliantlayer. In an embodiment, heat transfer/stress-reducing structure 110includes a compliant layer having a thickness less than about 1 micron.In another embodiment, heat transfer/stress-reducing structure 110 is adiamond layer and substrate 105 is a heat sink. In an embodiment, heattransfer/stress-reducing structure 110 includes a diamond layer having athickness greater than about 100 microns. In another embodiment, heattransfer/stress-reducing structure 110 includes a layer having islandsof diamond on substrate 105, where each island of diamond extends atmost to contact another island of diamond. In an embodiment, heattransfer/stress-reducing structure 110 includes a layer having islandsof diamonds in which each island of diamond does not contact anotherisland of diamond.

Electronic apparatus 100 may be formed by various embodiments of methodsfor forming device layer 115 with heat transfer/stress-reducingstructure 110 between device layer 115 and substrate 105. An embodimentof a method for forming an electronic device includes forming acompliant layer on a substrate, forming a diamond layer on the compliantlayer, and forming a device layer above the diamond layer. Depending onthe application, various forms of electronic devices can be constructedin the device layer.

FIGS. 2A-2D show stages associated with an embodiment for forming anelectronic apparatus having a device layer and a heattransfer/stress-reducing structure. FIG. 2A depicts a substrate 205 onwhich a heat transfer/stress-reducing structure and a device layer areformed in various embodiments. In an embodiment, substrate 205 is asemiconductor substrate. In an embodiment substrate 205 is a siliconsubstrate. Silicon substrate 205 may be a polycrystalline silicon handlewafer, which provides a relatively low cost element for themanufacturing process.

As depicted in FIG. 2B, a compliant layer 212 is formed on substrate205. In an embodiment, a polysilicon compliant layer is formed bychemical vapor deposition (CVD) processes. Alternately, the polysiliconcompliant layer may be formed by other methods as is known to thoseskilled in the art.

In another embodiment, forming compliant layer 212 includes forming adoped oxide compliant layer. A phosphorus doped oxide such as aphosphorous doped glass (PSG) may be formed as compliant layer 212.Alternately, a boron and phosphorous oxide such as a boron andphosphorous glass (BPSG) may be formed as compliant layer 212. Invarious embodiments, a PSG layer or a BPSG layer is formed on a siliconsubstrate.

FIG. 2C shows an embodiment of a formation of a diamond layer 214 oncompliant layer 212. In an embodiment, diamond layer 214 is deposited bya CVD process. In embodiment, diamond layer 214 is formed above asilicon substrate separated by compliant layer 212, which accommodatesthe stresses associated with CTE mismatch between diamond and silicon.This prevents or substantially reduces wafer warpage that would occurwhen diamond layers are deposited directly on silicon substrates. In anembodiment using a polysilicon compliant layer, the polysilicon layercan deform, in response to the stresses introduced in it by the CTEmismatch, by mechanisms of grain boundary sliding, rotation and otherstress relief mechanisms characteristic of polycrystalline materials. Inan embodiment using phosphorus and/or boron and phosphorous dopedoxides, such as PSG and/or BPSG, stress accommodation is a result ofviscoelastic flow of the oxide in response to stresses induced in thestructure. PSG and BPSG layers may be deposited by CVD processes. TheCVD processes include low temperature processes, typically around 400°C. Such compliant layers are typically soft and function as stressabsorbing buffer layers between diamond layer 214 and substrate 205.

FIG. 2D shows an embodiment of a formation of a device layer 215 ondiamond layer 214. Within device layer 215, a wide variety of devicescan be formed including, but not limited to, capacitors, diodes,transistors, memory devices, and opto-electronic devices. In anembodiment, device layer 215 is a semiconductor layer. In an embodiment,device layer 215 is a silicon layer. The silicon layer may includesingle crystalline silicon for device fabrication.

The thicknesses of compliant layer 212 may be limited to less than amicron to avoid introducing high thermal resistance between device layer215 and diamond layer 214. If compliant layer 212 is thicker than onemicron, an additional layer can be formed to provide stress relief suchas forming an oxide layer 216 between diamond layer 214 and substrate205. The oxide layer 216 may be formed on compliant layer 212 or betweencompliant layer 212 and substrate 205.

Active devices are fabricated in device layer 215. In an embodiment,once the processing of the wafer is completed, individual die forming anelectronic apparatus are cut from the completed wafer and each die isbonded to a heat sink. In an embodiment, substrate 205, complaint layer212, and oxide layer 216 are removed from the completed wafer, and a diehaving device layer 215 with active devices formed therein and thediamond layer 214 underneath is bonded to a heat sink. With substrate205, compliant layer 212, and oxide layer 216 removed, diamond layer214, having been formed in a stress-reducing structure, effectively actsas a heat transfer/stress-reducing structure disposed on a heat sinkacting as a substrate. Additionally, embodiments with a diamond layerthickness of 100 microns or greater and the diamond layer bonded to aheat sink with a silicon substrate removed perform with greater speed ascompared to a thinner diamond layer embedded on a silicon substrate withthe silicon substrate bonded to a heat sink.

FIG. 3 depicts an embodiment for formation a heattransfer/stress-reducing structure and a device layer includingadditional layers. The embodiment of FIG. 3 includes a substrate 305, adiamond layer 314, a device layer 315, and additional optional layers.In an embodiment, a polysilicon layer 318 is formed on diamond layer 314and a silicon oxide layer 320 is formed on the polysilicon layer 318. Inanother embodiment, a polysilicon layer 318 is formed on diamond layer314. In another embodiment, a silicon oxide layer 320 is formed ondiamond layer 314. In the various embodiments, device layer 315 formedabove diamond layer 314 may be a single crystal semiconductor layer. Inthe various embodiments, device layer 315 formed above diamond layer 314may be a single crystal silicon layer.

In an embodiment, further processing of the structure of FIG. 3 dependson whether compliant layer 312 is less than or greater than a specifiedthickness. FIG. 4A depicts an embodiment with compliant layer 312 lessthan a specified thickness, where a completed die is bonded to a heatsink 403. A structure having an embodiment of FIG. 3 is formed withoutoxide layer 316 between diamond layer 314 and substrate 305. Such astructure includes device layer 315, diamond layer 314, compliant layer312, and a silicon substrate 305 bonded to a heat sink 403. Compliantlayer 312 may include a polysilicon compliant layer, a phosphorus dopedoxide layer, or a boron and phosphorous doped oxide layer. In anembodiment, a thickness of about 1 micron is used as the specifiedthickness. Further, optional layers may be formed between device layer315 and diamond layer 314. Optional layers may include polysilicon layer318, silicon oxide layer 320, or silicon oxide layer 320 formed onpolysilicon layer 318.

FIG. 4B depicts an embodiment of a structure formed using a compliantlayer 312 greater than a specified thickness, where a completed die isbonded to a heat sink 402. As shown FIG. 3 oxide layer 316 is formedbetween diamond layer 314 and substrate 305, and active devices arefabricated in device layer 315. Substrate 305, complaint layer 312, andoxide layer 316 are removed from the completed wafer, and a die havingdevice layer 315 with active devices formed therein and diamond layer314 underneath is bonded to a heat sink 402. A thickness of about 100microns for diamond layer 314 provides sufficient support for devicelayer 315, when diamond layer 314 is bonded directly to heat sink 402.In an embodiment, a thickness of about 1 micron is used as the specifiedthickness. Further, optional layers may be formed between device layer315 and diamond layer 314. Optional layers may include polysilicon layer318, silicon oxide layer 320, or silicon oxide layer 3formed onpolysilicon layer 318.

FIGS. 5A-5G show stages associated with another embodiment for formingan electronic apparatus having a device layer and a heattransfer/stress-reducing structure. In an embodiment for forming heattransfer layer combined with device layers, stress reduction is providedby growing discontinuous layers from nucleation centers on a substratesuch that each layer extends to just meet, or contact, another layer. Inan embodiment, stress reduction depends upon the growth of discontinuouslayers as discrete islands of diamond nucleated on a substrate, whichjust meet when growth of the required thickness of diamond is achieved.In another embodiment, by growing discontinuous diamond layers asislands of diamond with narrow gaps between the islands of diamond, aheat transfer/stress-reducing structure is achieved by the gaps betweenthe diamond islands.

In an embodiment, a method for forming a heat transfer/stress-reducingstructure on a substrate includes forming diamond nucleation centers onthe substrate and forming an island of diamond on each nucleationcenter. The nucleation centers are separate from each other and eachisland of diamond grows on its nucleation center extending to, at most,contact another island of diamond.

FIG. 5A depicts a substrate 505 on which a heat transfer/stress-reducingstructure and a device layer are formed in various embodiments. In anembodiment substrate 505 is a semiconductor substrate. In an embodimentsubstrate 505 is a silicon substrate. Silicon substrate 505 may be apolycrystalline silicon handle wafer, which provides a relatively lowcost element for the manufacturing process.

Diamond nucleation on substrate 505 can be controlled by controlling thesurface characteristics of the substrate. Diamond typically does notgrow on polished, damage free surfaces. Consequently, prior to diamonddeposition the surface of the substrate 505 is treated to createlocalized surface damage 506. Abrading the surface of substrate 505 witha suitable abrasive, or immersing the substrate in an ultrasonic bathwith a suspension of an abrasive creates localized surface damage 506.In an embodiment, the thickness of localized surface damage 506 is lessthan about 0.5 microns.

FIG. 5B depicts an embodiment for forming selective nucleation centersincluding spinning photoresist 508 on the localized surface damage 506.Photoresist 508 is exposed thru a mask, and developed to mask selectiveregions of the localized surface damage 506 forming a patternedphotoresist.

FIG. 5C shows an embodiment in which the exposed parts of the localizedsurface damage 506 are etched to remove surface damage at theselocations. A pattern of pads results on substrate 505. Each pad includesa portion of photoresist 508 on a portion of localized surface damage506.

FIG. 5D depicts FIG. 5C with photoresist 508 removed. Localized surfacedamage 506 remaining after removing photoresist 508 forms nucleationcenters. FIG. 5E depicts forming islands of diamond 510 on nucleationcenters 506. In an embodiment, diamond is deposit by CVD. Each island ofdiamond 510 grows from its nucleation center extending horizontally andvertically until contacting another island of diamond.

FIG. 5F depicts an embodiment in which the islands of diamond 510 aregrown, at most, to extend to where an island of diamond just meetsanother island. The forming of these islands of diamond formdiscontinuous diamond layers having a discontinuity 511 along aninterface at which two islands of diamond just meet. Discontinuity 511forms as the islands of diamond contact in a mechanical manner ratherthan the islands coming together chemically. In an embodiment, growingislands of diamond 510 to the extent to which an island just contactsanother island provides a diamond layer having a thicknesses to about200 microns or less with individual islands of diamond which do not forma continuous layer. In an embodiment, diamond layers having individualdiamond islands separated from each other are grown having a thicknessranging from about 10 microns to about 200 microns using plasma enhancedCVD techniques.

A discontinuous diamond layer grown in the formation of a wafer fordevice fabrication in accordance with this embodiment avoids introducinghigh stresses in the wafer leading to wafer distortion that typicallyaccompany depositing continuous diamond layers across siliconsubstrates. Since a continuous layer is not grown the stress induced inthe substrate is limited to the stress induced by the individual islandsof diamond. Since these islands can be small compared to the total waferarea, the stress induced by the individual islands of diamond is notsufficient to locally distort the wafer. The regions where the islandsof diamond just meet provide a discontinuity in the diamond layer andcan thus function as stress accommodation, or stress-reducing, regionsin the structure.

FIG. 5G depicts an embodiment in which a device layer 515 is formedabove the islands of diamond 510. In an embodiment, a polysilicon layer518 is formed over the islands of diamond 510. After forming polysiliconlayer 518, the structure is polished. Device layer 515 is then formed onpolysilicon layer 518. In an embodiment, device layer 515 is asemiconductor layer. In an embodiment, device layer 515 is formed bybonding a single crystal silicon layer to polysilicon layer 518. Thesilicon layer bonded to polysilicon layer 518 may be a single crystalsilicon layer. In an embodiment, an oxide layer 520 is formed betweendevice layer 515 and polysilicon layer 518. In an embodiment, oxidelayer 520 is formed on a silicon layer prior to bonding the siliconlayer to polysilicon layer 518, where oxide layer 520 is disposedbetween silicon device layer 515 and polysilicon layer 518.

FIG. 6A depicts the formation of islands of diamond 610 on a substrate605 in which each island of diamond does not contact any other island ofdiamond. The resulting structure includes islands of diamond 610 forminga discontinuous diamond layer on substrate 605 with gaps 612 between theislands of diamond. Since a continuous layer is not grown the stressinduced in the substrate is limited to the stress induced by theindividual islands of diamond. Since these islands can be small comparedto the total wafer area the stress induced by the individual islands ofdiamond is not sufficient to locally distort the wafer. The gaps betweenthe islands of diamond provide a discontinuity in the diamond layer thatfunctions as stress accommodation, or stress-reducing, regions in thestructure.

FIG. 6B depicts the formation of a device layer 615 above the islands ofdiamond 610 of FIG. 6A in which each island of diamond does not contactany other island of diamond. In an embodiment, a polysilicon layer 618is formed over the islands of diamond 610. After forming polysiliconlayer 618, the structure is polished. Device layer 615 is then formed onpolysilicon layer 618. In an embodiment, device layer 615 is asemiconductor layer. In an embodiment, device layer 615 is formed bybonding a silicon layer to polysilicon layer 618. The silicon layerbonded to polysilicon layer 618 may be a single crystal silicon layer.In an embodiment, an oxide layer 620 is formed between device layer 615and polysilicon layer 618. In an embodiment, oxide layer 620 is formedon a silicon layer prior to bonding the silicon layer to polysiliconlayer 618, where oxide layer 620 is between silicon device layer 615 andpolysilicon layer 618.

In an embodiment, the material of substrate 505 or 605 can be replacedby a heat sink. Bonding a diamond layer formed as islands of diamond,510 or 610, to a heat sink may be accomplished by removing the substratematerial by grinding and bonding the diamond layer to the heat sink byconventional bonding techniques. Bonding such a semiconductor on diamondstructure in this manner forms the structure of FIG. 5G or 6B wheresubstrate 505 or 605 is a heat sink attached to a heattransfer/stress-reducing structure.

FIG. 7 illustrates a block diagram for a system 700 having devices usingan embodiment for a heat transfer/stress-reducing structure combinedwith a device layer. System 700 includes a controller 705, a bus 715,and an electronic apparatus 725, where bus 715 provides electricalconductivity between controller 705 and electronic apparatus 725. Invarious embodiments, controller 705 and/or electronic apparatus 725include an embodiment for a heat transfer/stress-reducing structurecombined with a device layer as previously discussed. In an embodiment,electronic system 700 includes a plurality of electronic apparatus usingan embodiment of a heat transfer/stress-reducing structure combined witha device layer. Electronic system 700 may include, but is not limitedto, information handling devices, wireless systems, telecommunicationsystems, fiber optic systems, electro-optic systems, and computers. Inan embodiment, controller 705 is a processor and electronic apparatus725 is a memory device.

Embodiments have been described herein to form apparatus having heattransfer/stress-reducing structures combined with active layers. In anembodiment, a diamond layer embedded between a semiconductor devicelayer and a silicon substrate, or other substrate, forms a semiconductoron diamond wafer for providing an additional heat transfer mechanism toan integrated circuit formed in the active layer. These integratedcircuits exhibit increased speed performance for structures havinglarger diamond layers. In an embodiment, to provide a heattransfer/stress-reducing structure, a compliant layer is interposedbetween a substrate and a diamond layer. The compliant layer providesstress relief and can include polysilicon, phosphorus doped oxides suchas PSG, or boron and phosphorus doped oxides such as BPSG. Theintroduction of a thin compliant material on a silicon wafer followed bythe deposition of a diamond layer on the compliant layer results in theCTE mismatch stresses being reduced by the compliant material, whichdeforms by viscoelastic flow. Providing this stress relief can preventdistortion of the wafer.

In another embodiment, a heat transfer/stress-reducing structure isprovided by selective nucleation centers on a silicon substrate, orother substrate, and forming diamond layers from the nucleation centersin which individual diamond islands are formed separated from eachother. The diamond islands are formed such that the vertical and lateralgrowth of the diamond islands continues, at most, until the diamondislands just meet. By forming islands of diamond rather than a singlecontinuous diamond layer, the differences in the CTE mismatch betweenthe substrate material and diamond are counteracted providing stressrelief and resulting in a flat wafer that can be further processed.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement that is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. This application isintended to cover any adaptations or variations of embodiments of thepresent invention. It is to be understood that the above description isintended to be illustrative, and not restrictive, and that thephraseology or terminology employed herein is for the purpose ofdescription and not of limitation. Combinations of the above embodimentsand other embodiments will be apparent to those of skill in the art uponreviewing the above description. The scope of the present inventionincludes any other applications in which embodiment of the abovestructures and fabrication methods are used. The scope of theembodiments of the present invention should be determined with referenceto the appended claims, along with the full scope of equivalents towhich such claims are entitled.

What is claimed is:
 1. A method comprising: forming a heattransfer/stress-reducing structure above a substrate; and forming adevice layer disposed above the heat transfer/stress-reducing structure.2. The method of claim 1, wherein forming a heattransfer/stress-reducing structure above a substrate includes: forming acompliant layer above the substrate; and forming a diamond layer abovethe compliant layer.
 3. The method of claim 2, wherein forming acompliant layer includes forming a polysilicon compliant layer or adoped oxide compliant layer.
 4. A method comprising: forming a heattransfer/stress-reducing structure above a substrate; forming a devicelayer disposed above the heat transfer/stress-reducing structure;wherein forming a heat transfer/stress-reducing structure above asubstrate includes: forming a compliant layer above the substrate; andforming a diamond layer above the compliant layer; wherein forming acompliant layer includes forming a polysilicon compliant layer or adoped oxide compliant layer; and wherein forming a doped oxide compliantlayer includes forming a phosphorus doped oxide, a boron and phosphorousdoped oxide, or a phosphorus doped oxide and a boron and phosphorousdoped oxide.
 5. A method comprising: forming a heattransfer/stress-reducing g structure above a substrate; forming a devicelayer disposed above the heat transfer/stress-reducing structure;wherein forming a heat transfer/stress-reducing structure above asubstrate includes: forming a compliant layer above the substrate; andforming a diamond layer above the compliant layer; and wherein forming acompliant layer includes forming the compliant layer having a thicknessless than about 1 micron.
 6. The method of claim 2, wherein the methodfurther includes removing the compliant layer and the substrate.
 7. Themethod of claim 5, wherein the method further includes bonding thediamond layer to a heat sink.
 8. The method of claim 2, wherein forminga diamond layer includes forming the diamond layer having a thicknessgreater than about 100 microns.
 9. A method comprising: forming a heattransfer/stress-reducing structure above a substrate; forming a devicelayer disposed above the heat transfer/stress-reducing structure; andwherein forming a heat transfer/stress-reducing structure above asubstrate includes: forming diamond nucleation centers above thesubstrate, each diamond nucleation center separated from each of theother diamond nucleation centers; and forming an island of diamond oneach diamond nucleation center, each island extending to at most contactanother island.
 10. The method of claim 9, wherein the method furtherincludes creating surface damage on the substrate prior to formingdiamond nucleation centers above the substrate.
 11. The method of claim9, wherein forming an island of diamond includes forming an island ofdiamond having a thickness ranging from about 10 microns to about 200microns.
 12. The method of claim 9, wherein forming an island of diamondon each diamond nucleation center includes forming an island of diamondon each diamond nucleation center such that each island does not contactanother island.
 13. The method of claim 9, wherein forming a devicelayer disposed above the heat transfer/stress-reducing structureincludes bonding a single crystal semiconductor layer disposed above theislands of diamond.
 14. The method of claim 13, wherein the methodfurther includes forming a polysilicon layer above the islands ofdiamond; and forming an oxide above the polysilicon layer.
 15. Themethod of claim 13, wherein bonding a single crystal semiconductor layerincludes bonding a single crystal semiconductor layer to a polysiliconlayer.
 16. An apparatus comprising: a substrate; a heattransfer/stress-reducing structure above the substrate; and a devicelayer disposed above the heat transfer/stress-reducing structure. 17.The apparatus of claim 16, wherein the heat transfer/stress-reducingstructure includes: a compliant layer; and a diamond layer above thecompliant layer.
 18. The apparatus of claim 17, wherein the substrateincludes silicon and the device layer includes single crystal silicon.19. An apparatus comprising: a substrate; a heattransfer/stress-reducing structure above the substrate; a device layerdisposed above the heat transfer/stress-reducing structure; wherein theheat transfer/stress-reducing structure includes: a compliant layer; anda diamond layer above the compliant layer; and wherein the compliantlayer has a thickness less than about 1 micron.
 20. The apparatus ofclaim 17, wherein the compliant layer is a polysilicon compliant layeror a doped oxide compliant layer.
 21. An apparatus comprising: asubstrate; a heat transfer/stress-reducing structure above thesubstrate; a device layer disposed above the heattransfer/stress-reducing structure; wherein the heattransfer/stress-reducing structure includes: a compliant layer; and adiamond layer above the compliant layer; wherein the compliant layer isa polysilicon compliant layer or a doped oxide compliant layer; andwherein the doped oxide compliant layer is a phosphorus doped oxide, aboron and phosphorous doped oxide, or a phosphorus doped oxide and aboron and phosphorous doped oxide.
 22. The apparatus of claim 16,wherein the heat transfer/stress-reducing structure includes a diamondlayer and the substrate is a heat sink.
 23. The apparatus of claim 22,wherein the diamond layer has a thickness greater than about 100microns.
 24. An apparatus comprising: a substrate; a heattransfer/stress-reducing structure above the substrate; a device layerdisposed above the heat transfer/stress-reducing structure; and whereinthe heat transfer/stress-reducing structure includes a layer havingislands of diamond, each island extends at most to contact anotherisland.
 25. The apparatus of claim 24, wherein each island of diamondhas a thickness ranging from about 10 microns to about 200 microns. 26.The apparatus of claim 24, further including a polysilicon layerdisposed above the islands of diamond.
 27. The apparatus of claim 24,further including an oxide above which the device layer is disposedabove the islands of diamond.
 28. The apparatus of claim 24, whereineach island of diamond does not contact another island.
 29. Theapparatus of claim 24, wherein the device layer is a single crystalsilicon layer.
 30. A system comprising: a controller; a bus; and anelectronic apparatus coupled to the controller by the bus, wherein atleast one of the controller and the electronic apparatus includes: asubstrate; a heat transfer/stress-reducing structure above thesubstrate; and a device layer disposed above the heattransfer/stress-reducing structure.
 31. The system of claim 30, whereinthe heat transfer/stress-reducing structure includes a compliant layerand a diamond layer above the compliant layer.
 32. A system comprising:a controller; a bus; an electronic apparatus coupled to the controllerby the bus, wherein at least one of the controller and the electronicapparatus includes: a substrate; a heat transfer/stress-reducingstructure above the substrate; and a device layer disposed above theheat transfer/stress-reducing structure; wherein the heattransfer/stress-reducing structure includes a compliant layer and adiamond layer above the compliant layer; and wherein the compliant layerhas a thickness less than about 1 micron.
 33. The system of claim 31,wherein the compliant layer is a polysilicon compliant layer or a dopedoxide compliant layer.
 34. The system of claim 30, wherein the heattransfer/stress-reducing structure is a diamond layer and the substrateis a heat sink.
 35. The system of claim 34, wherein the diamond layerhas a thickness greater than about 100 microns.
 36. A system comprising:a controller; a bus; an electronic apparatus coupled to the controllerby the bus, wherein at least one of the controller and the electronicapparatus includes: a substrate; a heat transfer/stress-reducingstructure above the substrate; and a device layer disposed above theheat transfer/stress-reducing structure; and wherein the heattransfer/stress-reducing structure includes a layer having islands ofdiamond, each island extends at most to contact another island.
 37. Thesystem of claim 36, wherein each island of diamond has a thicknessranging from about 10 microns to about 200 microns.
 38. The system ofclaim 36, further including a polysilicon layer disposed above theislands of diamond and an oxide disposed above the polysilicon layer.39. The system of claim 36, wherein each island of diamond does notcontact another island.